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Which instructions would you add to a z80, 6502 or similar 8-bit CPU if you had the chance?

barrel shifter

affine texture mapping innerloop fragments

spike: that is rather broad, can you be more specific?

Faster index register instructions for Z80, but ofcourse not necessary.

=>

I was thinking about which transfers r1 to r0 only when r1 is not zero. Nice for blitting sprites.

For the Z80:
- Fast clear memory instruction (like LDIR but faster and with (HL) replaced by an immediate value)
- Register rotation and shift of n bits in one pass
- Bit change (like RES and SET but with a XOR 1 effect)
- Multiplication but that's pushing things a bit too far :)

A multiplier will hardly be noticed (size wise) in a Z80, given the current dimension of transistors these days. The 8-bit ATmega series has multipliers, so putting one into a beefed-up Z80 is not so far-fetched.

In fact, the HD64180, which is a beefed-up Z80, has an onboard multiplier. That thing came out around 1985!

+1 for the index register instruction as well

I see what you mean.. Index instructions take 5 to 6 M-cycles and M-cycles are 3 to 6 clock cycles.. That thing is as slow as shit through a funnel.

The eZ80 is much better in that respect.

T80 soft CPU, that you can use in an FPGA-based computer, adds T-states artificially to imitate the real Z80 and 8080. Just by removing extra T-states it can be made much faster even at the same clock speed. Using static RAM is another speeding factor. Adding instructions is very much possible, too.

movbrain rrrola,ME

unpckxchg49bandcmpunlck

omgwtfbbq

65c816's stz would also be nice on a 6502

@svo: I've seen the T80; pretty nifty! Love your steam engine BTW.

OMG, which should be a half NOP ... nah :)

On a 6502 I could do with this kind of improvement:
- an instruction to set the address of the stack, would make it possible to use PHA/PLA anywhere in memory :)
- as Ferris wrote, STZ would be a nice addition, as well as TXY and TYX.
- a variant of INC and DEC (INA/DEA) working on the A register could be nice
- a new flag to disable the usage of the carry when using ROL and ROR (to have 8 bits rotations instead of 9 bits)

What Dbug said, plus a half nop like Weyland said.

dbug, I believe the 65c816 has txy and tyx. Anyway, my instruction would be XCQ: Exchange Carry and Quantum bit.

render3dscene

also:

print_real_edible_pizza_from_printer

Nah, that needs some improvement xeron.

mov al,3
print_real_edible_pizzas_from_printer al