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[ Wanted! ] Support organizers wanted for Network & Partymeister / Compo Team / Infodesk @ NORDLICHT 2026

Nordlicht 2026 is cancelled - or is it?? Unexpected real world events forced us to give up our initial schedule for Nordlicht Demoparty in July 2026. The location owner has since offered us an alternative date to host the party, just one weekend after the one we had originally aimed for. This would be Thursday 30th July to August 2nd 2026. While the current orga staff cast their votes to decide whether or not to go forward with planning Nordlicht for this year or skip until 2027, we're also...

[ scenemarket – latest listings ] Blood Omen: Legacy of Kain - Big Box Map

[Search] Other · Surprise me (by lutherplissken) I have a copy of Blood Omen: Legacy of Kain PC Big-Box, but it came without a map. I am looking for a copy of the map alone, or of course another copy of the Big-box, as long as it has a map too. --- Interested? Claim this item at https://scene.market/listings/38 — or list your own stuff for free at https://scene.market

[ Atariscne.org - News ] GCC for asm Experts (and C/C++ Intermediates) - Part 4

Register Allocation and the Cost Model

The m68k has 15 usable registers: d0-d7 and a0-a6 (a7 is the stack pointer, and sometimes a6 is also reserved as a frame pointer). For a CPU from 1979, this is actually quite generous; the 6502 has three, the Z80 and 8086 have seven or eight. So 15 should be plenty, right?

Not so fast. We have two register files with different capabilities. A pointer must be in an address register to dereference it. Most arithmetic must happen in data registers. For many use cases, we effectively have 7 or 8 registers to choose from, not 15. And if our function calls others, the ABI reserves the caller-clobbered registers, effectively leaving only ten registers: d3-d7/a2-a6 for free use with fastcall. When we run out, the allocator spills to the stack: on 68000, each 16-bit spill costs at least 16 cycles (8 to read, 8 to write back), and 32-bit values adds another 8. In a tight loop, it adds up fast.

When you write assembly, register allocation is intuition. You look at a routine and think: I need this value for the next three instructions, then I can reuse the register for something else. You juggle lifetimes in your head, naturally overlapping short-lived values. Teaching a computer this intuition is the fundamental challenge. The answer is to build a graph of which pseudo-registers are live simultaneously; two pseudos that overlap in lifetime interfere and cannot share a register. Then color the graph with K colors, one per available register, starting with the cheap caller-clobbered regs. When 19 pseudos from put_pixel compete for 15 registers, some will not fit — especially once you account for the data/address split — and those get spilled.

So how does GCC make the best of a difficult situation? 

[ Atariscne.org - News ] Revision 2026 shapshots

Here are a few snapshots from Revision, provided by Lotek Style and Samurai. thanks for sending those in!

Atarisceners spotted (from top left to down right): Havoc, Samurai, Havoc again (there can never be enough Havoc), NebulaH, Gunstick, Sgt Slayer (Atrocity!), JAC!, Lotek Style - not on the photo: Spiny and Havoc's friend with the sun glasses from last year ;p

A group photo may follow.

[ Atariscne.org - News ] Outline 2026 webpage online

The Outline Party 2026 will take place from May 14th to 17th! The freshly baked website is now available, so better get out your remote controls!

🔗 Outline 2026 website